CY7C1370D Spartan6 | Cypress Semiconductor
I'm trying to interface a CY7C1370D SRAM with a Spartan 6. I managed to have something working but I think is not properly done because sometimes the data read is corrupted.
FPGA clocks the SDRAM through an ODDR2.
Data goes to IOBUF. I would like to synchronize data with clock in order to have a precise relation between the two, especially in the read path.
Has anybody already done something similar?