the problem in writing to left port and reading from right port | Cypress Semiconductor
the problem in writing to left port and reading from right port
Hello,I run into a problem when using the dual-port SRAM CY7C0852V-133AC.
I want to write some datas to RAM arrays from the left port in write cycle and then read the datas from the right port in read cycle.I set the key signals(like OE、CE0、CE1、RW、CNT_MSK、CNTEN、ADS、CNTRST) accroding to the datasheet(attachment files for more details).
The result is unexpected.When writing 16 datas into array,the right port can read 16 datas accurately.But writing 41 datas into array,the right port can only read 26 datas instead of 41 datas.What's more,if writing 51 datas into array,the right port can only read 16 datas.Is the coincidence?
Please help me! Thank you very much!