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Decoupling and unused pins | Cypress Semiconductor

Decoupling and unused pins

Summary: 2 Replies, Latest post by rlacasse_1667151 on 13 Jul 2016 05:07 AM PDT
Verified Answers: 0
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rlacasse_1667151's picture
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2 posts

for the CYD36S72V18, what are your recommendations for power supply decoupling and for handling unused pins?

Thanks,

Rich

ajai's picture
Cypress Employee
78 posts

Not sure if you have had a look at our design guide for FullFlex devices - http://www.cypress.com/file/151216/download

It has the status of each of the pins which are not in use. 

For power supply- we recommend to have a decoupling capcitor for every pin and a bulk capacitor for every set of power rails. If there is a space constraint, we recommend to do a power integrity analysis to get the optimal value of bulk/decoupling capacitors array.

rlacasse_1667151's picture
User
2 posts

Hi Ajai,

Thanks for your help.  I had found the design guide.

I guess I did not ask my first question very well.  Let's say I am using the left data ports as inputs only and that I need only 70 of the 72 bits.  What should I do with the two unused bits - tie them high via a resistor, tie them to ground or leave them open?

With respect to decoupling, do you recommend any particular value capacitors?

Thanks,

rich

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