EZadc 5.3 Comments | Cypress Semiconductor
EZadc 5.3 Comments
1) Sample rate is shown on first instance as 0.121, that
would be 0.121 what ? Oersteds, grams, Ksps......No units
2) When place is first initiated, user presented with choice
of 1 or two modulator architecture, but in Description no
comments as to advantages/disadvantages of the use of 1 or 2
modulators. Should be a bullet list of advantages/disadvatages,
tradeoffs. For example dual modulator requires 2 columns, and
clks in both columns from same source. That is potentially a dis-
advatage. Longer latency in flushing filters, lower SPS.....blah
If user reads datasheet ( we can only hope ) then life is good.
But point is a quick summary when placing module, for those that
3) Descriptive info, nowhere does it indicate a PGA will also be
placed. And that "Buffer Gain" is PGA gain, not an amp in ADC.
4) A comment on place screen, this is a R-R inout solution, or not.
5) Maybe set up a novice EE tester, you tell him to place this
module, then watch and record all his questions, might be very
informative. Then revise tool to handle most of the inquiries
relating to use. Just a thought, basically marketing research
in a technical sense.
PWM Comments -
1) Why no 24 or 32 bit simple PWM ? You have the counter modules
for same.......I suppose we could use respective timers to get
the equiv PWM resolution. Additionally when using a pWM as a DAC,
how to compute ripple vs 1'st or 2'ond order LP filters, how to
get to "effective" resolution and settling time for a given filter.