Warp verilog include path settings | Cypress Semiconductor
Warp verilog include path settings
at this time I write a multi module implementation of a PSoC component in verilog. The top level module instanciates here 2 other modules which are separated into 2 different files (to test these sub modules with there own test bench). Using verilog's `include directive these works for modelsim, but warp doesn't find the files finaly even if there are in the same directory as the top level module. How can I extend/set the include path of warp?