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UDB Editor - Known 'Problems' & Gotcha's | Cypress Semiconductor

UDB Editor - Known 'Problems' & Gotcha's

Summary: 3 Replies, Latest post by tdu on 08 Jan 2014 06:25 PM PST
Verified Answers: 0
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user_274749305's picture
76 posts

I've tried to read through all the posts in the forum that appear to discuss the UDB Editor in PSOC Creator 3.0

I didn't "reply" to any of them, since no ONE has been designated a central clearinghouse for trouble reports on the UDB Editor.

I apologize for the post, please delete if wrong type/format.

I've seen posts from some about specific problems and some requests of "how do we report problems". I'm not sure I, or others, understand any tracking or support procedure for something like this. I don't think we need to open a "MyCase" for each individual problem and I know of no way of seeing all open or closed bug reports to avoid duplication. If you want to post them to this thread for Robyn to forward to Development team or for Nick (NSF-Cypress?) to reply to.

I've seen some posts by Dana, psoc73, bob, nick, spider... etc but think most of my issues/questions have not been addressed.

I came late to PSOC Creator 3.0 (PC 3.0)because we are primarily working with Christmas Lighting products and my busy season has just ended. I couldn't take a chance of working with a new environment with my production code late in the season.

All in all I think PC 3.0 is a VAST improvement and applaud Cypress on this major release.

Once over the learning curve I find the UDB Editor to be a great tool in the making. I don't think it is there yet, but hopefully the development team can finish it up soon.

In the tutorials they talk about "advanced features can then be added by copying the verilog ..." or something close to that. But they never discuss what they are calling advanced.

Here is a short list of the 'problems' I'm having so far:

1) I can't locate any way to control most of the features of the FIFOs. I see several FIFO properties but can't find the way to change the FIFO to input vs output (bus vs udb sourcing). Am i overlooking something. Having to copy the verilog and modify it will be a development headache.

2) If you add a control or status register to the USB Design DON'T delete the unused bits for 'cleanliness'. If you do you will get a 'Net_1' undefined message. Just leave unused bits there.

3) If you add a Count7 register I can set some of the inputs (reset, enable, etc.) but can't set the clock, and more importantly I can find no way to USE the Count7_tc output. I believe the verilog is being generated correctly. It makes a wire and adds it to the Count7 module definition but if I try to use the signal as part of ANY expression then I get an error saying it doesn't exist and, of course, the verilog becomes non-generated. Take out the expression and the verilog comes back. So I think it is an internal table lookup problem and not a real generation of verilog problem.

#1 is major IMHO, #2 is cosmetic, #3 is major. Altogether I don't see how I can use the UDB Editor for production code until these types of problems are fixed. I've invested a lot of time over the holidays learning the GUI and visually designing the state machines and examining the generated verilog to see how they do it. It is BEAUTIFUL and VERY powerful, and I want it to work soon!!!



user_274749305's picture
76 posts

oops - Bob and Nick have already discussed the Count7_tc problem. but no mention of the clock input.


user_1377889's picture
9265 posts


I had the feeling, that Cypress started the UDB-Edit software to get a look whether this effort pays and will continue (or not) its improvement. Same seems to be with the Digital Filter Block and its assembly capabilities. Compared to the questions asked this module is only rarely used and the effort in improving it is small.

Concerning the UDB-Editor: The first roll-out presented something just sparingly usable (and after some more questions) Cypress reveilled that an update will come with the next Creator release. The next Creator update will probably be rather soon (February?), but I do not have an announcement for the next release yet. So it might be very good practice to collect all the bugs and flaws and report them to get this VERY useful part of the software improved.

Do not forget: There are some capable Cypress engineers to help you out with work-arounds when you file a MyCase.


Happy coding, happy 2014


tdu's picture
Cypress Employee
3 posts


Answer to your question about the clock. All of the "pieces" (lack of a better word) of a UDB editor design are all clocked off the same clock. So if you have a datapath, a Count7, and a control register all will use the same clock. When you generate the component symbol it will create a clock input for you. 

If you wanted your Count7 to run at a different clock rate then you could create another UDB component and run "wires" between your two components. This however, is annoying!

For the first release it was decided that everything would have one clock to keep it simple and clean. I feel that it should have the option to have mulitple clocks for the different "pieces". Hopefully we can push to have that feature added in later releases.

As for the FIFOs let me look at it a little more. I believe that the editor will automatically set the direction of the FIFO based on how you configure it in the editor, but I would need to look at it more to confirm.


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