Trouble with static timing analysis | Cypress Semiconductor
Trouble with static timing analysis
Why is the static timing analysis affected by the component (symbolic) name?
I have an ISR in the schematic, when I call it "CUT_ISR", the static timing analysis returns a warning "setup time violation" but when I call it "UT_ISR" all goes fine and I receive no warning.
I'm really scared about that :( because I don't know which are the "optimum" names for the components that will allow the maximum working clock frequency.