Strange static analysis warning: | Cypress Semiconductor
Strange static analysis warning:
I have a somewhat strange issue with the static analysis. I basically need a 24bit-counter which is driven by an internal clock (MASTER/3). Since it is 24 bits, it needs to be UDB-based, and therefore needs a sync clock. For that I also use an internal clock (MASTER/1). Now I get the warning that there is a clock path between these two clock, and they are not synchronized:
Warning: sta.M0019: Design01_timing.html: Warning-1350: Path(s) exist between clocks Clock_1(routed) and Clock_2, but the clocks are not synchronous to each other: (ClockBlock/dclk_0, \Counter_1:CounterUDB:sC24:counterdp:u2\/ci) (File=D:\dev\psoc\freqmeter\Design01.cydsn\codegentemp\Design01_timing.html)
Warning: sta.M0019: Design01_timing.html: Warning-1366: Setup time violation found in a path from clock ( Clock_2 ) to clock ( Clock_2 ). (File=D:\dev\psoc\freqmeter\Design01.cydsn\codegentemp\Design01_timing.html)
But both clocks are set to 'synced'. This is part of a larger project, but I have reduced it to this simple example - see the attachement.
What is the problem here, and how can I avoid it?