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Strange issue with 48 MHz clock and UDB PWM component | Cypress Semiconductor

Strange issue with 48 MHz clock and UDB PWM component

Summary: 1 Reply, Latest post by Bob Marlowe on 15 Sep 2016 05:09 AM PDT
Verified Answers: 0
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user_466193552's picture
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So I was using a PSoC 4200L chip, and when I was using a PWM, I cannot set the HFCLK to 48 MHz. However, to use the USB component, it requires me to use 48 MHz. When I build the project with the 48 MHz clock, it gives me a message saying

Warning-1366: Setup time violation found in a path from clock ( clk1m ) to clock ( clkphase ).

When I double click this, the violation appears to be the maximum frequency for HFCLK is only 29.8 MHz. 

I have attached the project. Appreciate your help!

 

 

user_1377889's picture
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10428 posts

Double post. Please follow up here.

 

Bob

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