Strange issue with 48 MHz clock and UDB PWM component | Cypress Semiconductor
Strange issue with 48 MHz clock and UDB PWM component
So I was using a PSoC 4200L chip, and when I was using a PWM, I cannot set the HFCLK to 48 MHz. However, to use the USB component, it requires me to use 48 MHz. When I build the project with the 48 MHz clock, it gives me a message saying
Warning-1366: Setup time violation found in a path from clock ( clk1m ) to clock ( clkphase ).
When I double click this, the violation appears to be the maximum frequency for HFCLK is only 29.8 MHz.
I have attached the project. Appreciate your help!