SPI Slave drops a byte from TX FIFO? | Cypress Semiconductor
SPI Slave drops a byte from TX FIFO?
I'm using the SPIS component with an interrupt handler on "Interrupt On Rx FIFO Not Empty". The master performs two-byte writes before pulling the slave select line high again.
For testing purposes, after I receive the first byte, I send out 0x55 on MISO. After I recieve the second byte, I put 0x77 in the TX FIFO. This works fine except for the very first SPIS RX interrupt--in this case, one 0x77 that I put in the TX FIFO just isn't sent out. Notice in the spi.png file, there's a 0x55 following a 0x55 where 0x77 should be intervening.
The RX interrupt handler is as follows:
static uint8 toggle = 0;
uint8 data = SPIS_1_ReadRxData();
uint8 status = SPIS_1_ReadRxStatus();
if (toggle == 0)
toggle = ~toggle;
Any idea why one of the bytes in the FIFO isn't getting sent out? I also uploaded the project itself.