Settling Time Incomplete Specs | Cypress Semiconductor
Settling Time Incomplete Specs
In the module datasheets you have the following issues -
1) Analog mux, you give a selttling time with out any attached resolution. There
should be a table of times vs resolution to 20 bits, down to 8 bits.
2) S/H, same problem, you only spec to 1% which is ~ 7 bits, not really a useable
number for worst case design. Again a table from 8 to 20 bits.
3) You should show in applicable datasheets how to calc settling time to worst
case for a first order R-C network so users can calc their own design. Calc to 1/2 LSB.