See generated Verilog ? | Cypress Semiconductor
See generated Verilog ?
Summary: 2 Replies, Latest post by srim on 06 Feb 2012 12:47 AM PST
Verified Answers: 0
04 Feb 2012 09:23 AM PST#1
When I place a digital component, and build the project, does that component generate a Verilog file ? Is it possible to see this verilog file ?