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See generated Verilog ? | Cypress Semiconductor

See generated Verilog ?

Summary: 2 Replies, Latest post by srim on 06 Feb 2012 12:47 AM PST
Verified Answers: 0
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Rocketmagnet's picture
131 posts

Hi all,


When I place a digital component, and build the project, does that component generate a Verilog file ?  Is it possible to see this verilog file ?


Many thanks

Hugo Elias


dasg's picture
Cypress Employee
730 posts

Hi Hugo Elias,


You can view the Verilog source file of the UDB based components from the CyComponentLibrary.Lib.

You can access this from your installation folder. In my case, the location turns out to be

C:\Program Files\Cypress\PSoC Creator\2.0\PSoC Creator\psoc\content\CyComponentLibrary\CyComponentLibrary.cylib


A word of caution! The C files, Header files and the Verilog files if manipulated here will change forever. The change done, if any, will reflect in the Creator generated files. However, you can view the Verilog file to understand its implementation.

srim's picture
Cypress Employee
111 posts

Hello Hugo Elias,

 As far as I know, There is also a * .v file generated in codegentemp folder that contains the verilog code generated. 

~ srim





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