PSoC5 UART RTS Flow Control | Cypress Semiconductor
PSoC5 UART RTS Flow Control
I am wondering about the Request To Send (RTS) output from the UART component.
The data sheet says it is de-asserted when the input buffer is full, but it doesn't say when it is re-asserted; does anyone know?
This is related to a bigger issue that may warrent an enhancement to the UART Component...
If the device that I am trying to hold off still sends the byte in progress, or maybe even a couple more, before it can honor the RTS line, then I miss those bytes. For an experiment I am going to manually control RTS to de-assert when the buffer is 80% full.
If the device that I am receiving from has some delay before starting again (assuming RTS is re-asserted when the buffer is empty) then I timeout on no data input. For my experiment I will re-assert RTS when the buffer is 20% full.
Any thoughts on this will be appreciated.