PSOC Creator 3.0 Timing Analysis: Negative Frequency? | Cypress Semiconductor
PSOC Creator 3.0 Timing Analysis: Negative Frequency?
I am working on a design in Creator 3.0 using a PSOC5LP that uses internally generated 60MHz clock or clocks.
(3.7V on all Vdds and 0-85/125 temperature range.)
Occasionally the Static Timing Analysis, under Clock Summary says the maximum frequency for a certain clock is a NEGATIVE NUMBER!
What does this mean, other than it does not like the design?
PS: Is there a design recommendations document that addresses things like whether it is better to use one clock or multiple clocks of the same frequency? Or best methods for preventing hold time violations? I seem to get inconsistent or counter-intuitive results when I try simplifying my logic with the Static Timing Analysis.