Can i use any Component in my verilog code by instantiating it?
I think you can only instantiate component which are defined in Verilog themselves. This should everything defined as 'primitive'.
So, I can instantiate only components with .v file, right?
Please, help me with this. I'm trying to instantiate "cy_dffe_v1_0" just for a example and i'm getting this error:
"M0120:Can't find 'cy_dffe_v1_0" in library 'work' with path 'lcpsoc3'.
the DFFs are defined in rtl.v, as
module cy_dff (d, clk, q);
So maybe you want to include that one? (The definition of cy_dffe_v1_0 is empty, if you look at the file...)
Thank you for your help.