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How to split Firmware and Component Creation Code (Verilog) | Cypress Semiconductor

How to split Firmware and Component Creation Code (Verilog)

Summary: 1 Reply, Latest post by Bob Marlowe on 03 Feb 2015 08:47 AM PST
Verified Answers: 0
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muratcakmak's picture
8 posts

Hi all,

I am newbie and sorry If the same question was asked before.

As I understood, PSoC Creator creates hex file from Firmware and Verilog codes (for Programmable HW Blocks). 

I want to create a HW Design and want to pack it. After that I want to develop firmware in different environments. I dont mean export PSoC Project to Eclipse or uVision. I want to port an open source project to PSoC5 and it has own build environment. I want to implement PSoC specific modules for open source project and distribute it with pre-defined HW Design. 

Is it possible? 

Is there any document that explains hex file creation and Firmware and Programmable HW Block code relations?




user_1377889's picture
9283 posts

Since Creator seems to be the only software that "knows" PSoCs it will be difficult to specify the hardware components and wiring your project uses. There are some PSoC Register TRMs (example here that shows that the complete hardware description is done by setting bits in a register area. This is the job of the "Fitter" part of PSoC and seems to be something complicated according to the long run-time of that phase.



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