How to specify false paths | Cypress Semiconductor
How to specify false paths
Is there any way of specifying false paths or other timing exceptions for Warp synthesis in a custom component PSoC design?
I seem to have run into a bit of trouble meeting the timing requirements for a PSoC 5LP design. Specifically the path from the output on a bidirectional GPIO pin back to the input pushes the synthesis over the edge. The input and the output logic are only used in separate modes of the system however so I am hoping to declare this as a false path without the synthesis failing or expending resources optimizing for it.
I do know how to work around the issue with additional buffering however the margins of the design are getting alarmingly tight so any cycles shaved off would be a boon.
Admittedly I am a programmer still very much struggling to get to grips with this HDL business and may well be going about designing and optimizing it all wrong. Incidentally any tips for suitable reading matter on this subject would be much appreciated, ranging from specific PSoC tricks to general hardware design principles.