Is it possible to connect the fragments of severalBUS
At least not making it looking much better than your original solution. What you can do:
I tested this, and the busses still kept their original names.
Correction: I just tried to build this project, and got the error: "CRL and SR are connected and have inconsistent base names".
So this doesn't work, and seems not to be supported. But in the end this makes sense that way - nets need to have consistent names to ensure proper routing.
I would propose you create a bus containing the data lines and th4 clock. Then you can connect only the lines you really need, like you would do in any other schematics editor.
thanks. It is a pity that I can not assign a common name of several conductors in different bus.
Information for Technical Support:
When i edit bus and has error - error remains even after removal of the bus.
I have to close the project and download it again.
An example of such an error is attached below.
A very unusual way to get out of this naming-problem could be to write a custom-component and hoping for the optimizer.
Yes, that approach works, see attached project
Thank you, Bob. I tried to change your project, but I have certainly failed.
This "persistent error" problem happens not only with busses, but with serveral others too. Sometimes they even persist aver re-opening the project. And there is no way to clear the error list :(
One of the errors you get has to do with connecting an input pin to the output of the status register, same with the control reg.
Control has inputs, Status has outputs...
... and connecting more than 1 signal to form a bus does not work within a component, but you may make the connection on the schematic by specifying the signal to be part of the bus. I would suggest you to correct your Input/Output problem and post your resulting project again.
Sorry, my last posts were rubbish!
Corrected project attached.