creating 50nsec delay with PSoC3 logic cells | Cypress Semiconductor
creating 50nsec delay with PSoC3 logic cells
I'm creating a range of pulse signals in response to an external trigger (stretching, delaying, etc.) to replace some expensive FPGA functions w/PSoC3 logic cells. I have most in good shape, but need to generate a simple 50nsec delay of the external trigger (an 80nsec pulse), but cannot use any clock based devices due to introduced jitter (ie: counters, timers, SRFF, etc.). With the input pin in Transparent mode, I see about 20nsec delay through any gate (inverter, AN, OR, etc.), but cannot string any together to make that larger. Even adding output pins in between multiple gates, the compiler is too smart and I never see an increased delay. This needs to be done in hardware (ie: no code involved, registers, etc.).
Anyone have any tips on creating a small delay in h/w?
Thanks - Steve