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Can i use verilog file as top design in PSOC Creator? | Cypress Semiconductor

Can i use verilog file as top design in PSOC Creator?

Summary: 2 Replies, Latest post by gwb982_1673746 on 30 Nov 2016 04:13 PM PST
Verified Answers: 1
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gwb982_1673746's picture
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2 posts

Can i use verilog file as top design in PSOC Creator? thank u very much!

user_1377889's picture
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9581 posts

Welcome in the forum.

The topdesign is a file that collects and wires components only, thus defining your complete project. Verilog can be used to build your own components.

 

Bob

gwb982_1673746's picture
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2 posts

tks! 

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