UDB 2nd Order Cascaded Integrator Comb (CIC) Decimator. Pairs very nicely with the SC/CT DelSig modulator for a rudimentary ADC | Cypress Semiconductor
UDB 2nd Order Cascaded Integrator Comb (CIC) Decimator. Pairs very nicely with the SC/CT DelSig modulator for a rudimentary ADC
This memo documents and distributes a 2nd order Cascaded Intergrator Comb (CIC) decimation filter implemented in a 16 bit datapath (also called a Sinc^2 decimator). The decimator supports decimation rates as low as 2 and as high as 128, producing effective resolutions of up to 10.5 bits when used with a first order Delta Sigma modulator and raw results as large as +/- 16,384, the equivalent of a signed 15 bit number at a decimation rate of 128. The decimator requires a maximum of 8 clock cycles to complete a calculation, requiring a clock 8 times faster than the modulator clock. When combined with the SC/CT modulator at the maximum modulator clock rate of 4 Mhz, the decimator requires a 32 Mhz clock, resulting in an output sample rate from 363 Ksps with 5 bits of effective resolution, down to 31 Ksps with 10 bits of effective resolution. The decimator component includes a DMA capability file for simplifying the use of DMA with the decimator. Start() is the only API required to use the decimator.
This component is not "complete" since it lacks an official datasheet, but I am not sure when I get around to writing that so I decided to publish this "As is" since something is better than nothing. The zip file include lots of info on how I made the component, as well as something that will pass as a rudimentary datasheet. The zip file also includes the component in a .cycomp archive, an example project bundle, a scan of the UDB datapath instructions and the python simulation.