SPI Master with a dedicated DMA drq line | Cypress Semiconductor
SPI Master with a dedicated DMA drq line
I shamelessly modified the stock SPI master 2.40 component in the catalog to support large DMA transfers more easily. The only reference I could find to send data via SPI and DMA was to use the interrupt line and then an indexed DMA to clear the interupt flag (CE56273). Probably there are other solutions but I did not come across them in my short search.
This method seemed complicated as I have a 4kB frame buffer I want to repeatedly send to a display without worrying too much. Thus, I added two lines of verilog to the Base Spi component:
output wire tx_drq //in the module descriptor for module B_SPI_Master_v2_40_DMA just to indicate an extra output
as well as:
assign tx_drq = dpMOSI_fifo_empty;
All this does is bring out the FIFO empty signal to make it accessible to a level sensitive dma component. There is an extra pin brought out for the base and the master component. All the rest is left the same. Attached you can find the workspace with the custom components.
It is happily transfering 4096 bytes across to my display now (which is so annoyingly one byte larger than one TD can handle!). This project is for a psoc5.
Any input is appreciated.