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How to make DDS module | Cypress Semiconductor

How to make DDS module

Summary: 42 Replies, Latest post by JLS1 on 21 Oct 2013 04:57 PM PDT
Verified Answers: 14
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user_119377051's picture
866 posts

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Hello PSoCers

I am willing to submit
this article.

Still getting started
this component division.

i am afraid of some
rudeness of mine.

don't know the rule of
this division yet.


In my practice, DDS
module become working.

There are many items to
have improvements.

I want to listen to how
to get more efficiency.

Want to listen to
critique from everyone


I have been work with
Xilinx CPLDs,

those works are mainly
schematic-base design.

I am new to PSOC CPLD
and Warp-Verilog.


Keep it up rolling !

user_119377051's picture
866 posts

 This is the component export 

user_119377051's picture
866 posts
user_119377051's picture
866 posts


user_119377051's picture
866 posts


Frequency range : 1mHz to 10KHz (sine wave)

Frequency resolution : 1mHz nominal

Test design is work with PSoC5LP in PSoC4 Pioneer Kit

(bootable composition) 

user_119377051's picture
866 posts

 I was using Creator2.2 sp1 

Because 3.0 intelligent helper has trouble in component design,

Treat of Instance name space.

However that seems working well finally. 

user_78878863's picture
2553 posts

I can confirm it at least compiles in Creator 3.0.

What is the difference to the DDS project of PSoC Sensei? Your component seem to have simpler setup, but creates only sine waves.

What is the frequency step resolution your DDS component achieves? Is it 'DDS frequency / 2^32' (the verilog looks like your are using a 32 bit phase accumulator)?

Stub for 336561766's picture
1 post

I would describe easy operation of test bench.

This is using PSoC5LP on P4 Pioneer Kit as bootloadable device.

It is very simple.

1) Connect the USB cable while pressing the SW1:reset button

The status LED(green) start blinking

2) When load the program: Use /Tools/Bootloader Host

instead of PSoC Programmer.

3) Ensure Port Filters, USB Device: VID=0x04B4 PID=0xF13B

4) Load bootable object [P5LP_DDS.cyacd] from MortexM3 directory, And write it.

5) Ensure the Jumper plug J13 to ON

If not, Pioneer Kit return to bootable status every time.

If you are using without Pioneer KIt,

Change project setting, Code Generation/Application type to "Normal" and Need to some refine cydwr, System Setting.

When you want to revert default setting of Pioneer Kit

It is also easy, PSoC programmer doing that.

In detail, See user guide of Pioneer Kit, section 6: Advanced Section


user_119377051's picture
866 posts

Haw! I am becoming The Invisible Man

I like it.

user_200706552's picture
124 posts

 Great project many thanks :-)


Please help


When compile with Creator 2.2 SP6 working great but this peoject open and recompile with Creator 3.0 not working (compilling without errors but bootloader not working only fast blinking programming led)


Thanks help.



user_119377051's picture
866 posts

Hello JLS1 welcome

Basically, this was working on my Creator3.0

But I worry about some error display at component design.

I was publish on Creator2.0

So, I have a Creator 3.0 version, I can be uploading.

But please wait for awhile, I have to ensure the bootloading

and Upload it tommorow.

Thank you.

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