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DFB assembler and (Significantly) Improved Simulator component | Cypress Semiconductor

DFB assembler and (Significantly) Improved Simulator component

Summary: 38 Replies, Latest post by Junk_1683616 on 14 Dec 2017 10:27 AM PST
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kees's picture
Cypress Employee
65 posts

 This was a joint component improvement effort by myself and Dan Sweet (DRSW, a fellow apps engineer).

 

We were doing some development with the DFB and came to realize what a frustrating experience it was to learn and program the DFB.  The documentation needs a significant overhaul, but in the meantime, a much better simulator was an absolute must.  Dan and I spent weeks pouring over documents, memos and other information and learning everything we could about the DFB.  The fruits of our labor allowed us to climb into the simulator and provide *significantly* more information to the intrepid DFB programmer when using the simulator.  The new simulator now shows:

 

  • A1 / B1 mux ouptut and mux arm selection 
  • ACU ram address, ACU A / B operation, A / B RAM write and read addresses and write enable signal
  • A2 / B2 mux output and mux arm selection
  • Mac A / B inputs, operation and output (upper 24 bits of accumulator)
  • A3 / B3 mux outputs and mux arm selection
  • ALU A / B inputs, operation and output
  • shifter operation and output
  • reads from holding registers, writes to output registers and A / B RAM

 

The simulation also includes a significantly expanded simulation properties window that shows:

 

  • ACU A / B internal registers (LREG, MREG, FREG, REG, mod enable)
  • current jump conditions (in1, in2, acuaeq, acubeq, dpeq, dpsign, dpthresh, global jump enable, semaphore jump enable)
  • ALU internal variables (rounding flag, saturation enable, saturation flag, squelch count, squelch value)
  • global input signals (writeable)
  • semaphore values (readable / writeable)
  • ACU A / B RAM contents
  • Datapath A / B RAM contents
  • Internal execuation values (finite state machine index, CSTORE RAM A / B selection and index) [these values are not needed by the DFB programmer, they are left in for advanced users and assembler debugging]

 

The attached zip archive includes the component in a library, as well as an archive of the component exported to a .cycomp archive using the component export feature.  The archive also includes some memos that talk about code blocks and instruction pipelining, which helps a lot when trying to write code for the heavily pipelined DFB.

 

An important note, because of the pipelining, an opcode will not necessarily execute immediately.  It may occur 1, 2 or 3 instructions later.  This is what makes the simulator so valuable.  you can observe when the opcodes execute and quickly determine if your data is where it needs to be when the opcode is ready.

kees's picture
Cypress Employee
65 posts

 The previous ZIP archive had problems, use this archive.
 

Wendell's picture
User
3 posts

 I'm trying to load up the advanced assembler.

But it looks like something in the ZIP file is wrong.   When I try to import it...

 

Error Message in .jpg file....

 

 

 

Attachments: 
kees's picture
Cypress Employee
65 posts

Did you try using the second zip file?

Wendell's picture
User
3 posts

 Yes, I was using the second zip file (Tried the first one after that didn't work.)

kees's picture
Cypress Employee
65 posts

 ok, it looks like creator was not bundling up the cycomp file properly.  I have attached a project with the improved DFB assembler imported into the project and I have verified the DLL is present.

 

Please give this a try and let me know if it works for you.

Wendell's picture
User
3 posts

 Thanks,

That works for me.

 

ilya's picture
User
1 post

 Is there a way to preload the values into the ACU ram and the datapath rams for simulation.

Are there any example assembly files

 

Thanks In advance

kees's picture
Cypress Employee
65 posts

 "Is there a way to preload the values into the ACU ram and the datapath rams for simulation.

Are there any example assembly files"

 

Great questions!  I'll do what I can here:

 

As for preloading the ACU and Data RAMS, use the following syntax:

 

area acu

org o

dw 0xaabb

dw 0xaabb

...

 

This defines ACU memory (Area acu) starting at location zero (org 0).  The ACU is split into an A and a B side with each side having 7 bits with the MSb of each byte is ignored.  To be a bit more helpful with and example, if I wanted to load ACU side A location 0 with a value of 0x03 and ACU side B location zero with the maximum value of 0x7F, I would do the following:

 

area acu

org 0

dw 0x037f

 

I can then add more "dw 0xaabb" values to fill in the rest of the ACU.  any undefined ACU locations will be filled with the default value of 0x00.

 

To fill in the data RAMs, use the following syntax:

 

area data_a

org 0

dw 0x000000

dw 0x000000

...

 

As for example scripts, I'll provide one of my scripits from my DFB folder titled "MACC and ALU Tests2".  This will get you some of the basic information:

 

init:

acu(clear, clear) dmux(srm, srm) alu(hold) mac(hold)

acu(loadm, loadm) addr(3) dmux(srm, srm) alu(hold) mac(hold)

acu(hold, hold) dmux(srm, srm) alu(hold) mac(hold) jmpl(eob, loop)


loop:

acu(hold, hold) dmux(srm, srm) alu(seta) mac(hold)

acu(hold, hold) dmux(srm, srm) alu(seta) mac(hold)

acu(write, write) addr(2) dmux(srm, srm) alu(seta) mac(hold)

acu(read, read) addr(2) dmux(srm, srm) alu(seta) mac(hold)

acu(hold, hold) dmux(srm, srm) alu(seta) mac(hold)

acu(hold, hold) dmux(srm, srm) alu(seta) mac(hold)

acu(hold, hold) dmux(srm, srm) alu(seta) mac(hold)

acu(hold, hold) dmux(srm, srm) alu(seta) mac(hold)

acu(hold, hold) dmux(srm, srm) alu(seta) mac(hold)

acu(hold, hold) dmux(srm, srm) alu(seta) mac(hold)

acu(hold, hold) dmux(srm, srm) alu(seta) mac(hold)

acu(hold, hold) dmux(srm, srm) alu(seta) mac(hold)

acu(hold, hold) dmux(srm, srm) alu(seta) mac(hold)

acu(hold, hold) dmux(srm, srm) alu(seta) mac(hold)

acu(hold, hold) dmux(srm, srm) alu(seta) mac(hold)

acu(hold, hold) dmux(srm, srm) alu(seta) mac(hold)

acu(hold, hold) dmux(srm, srm) alu(seta) mac(hold)

acu(hold, hold) dmux(srm, srm) alu(seta) mac(hold) jmpl(dpeq, loop)



area acu

org 0

dw 0x0000

dw 0x0101

dw 0x0202

dw 0x0303


area data_a

org 0

dw 0x7ff000

dw 0x000f00

dw 0x03ff00

dw 0x001000


area data_b

org 0

dw 0x7ff000

dw 0x000f00

dw 0x03ff00

dw 0x001000

kees's picture
Cypress Employee
65 posts

 Forgot to mention that for data RAM side B, you use a similiar syntax for side a:

area data_b
org 0
dw 0x000000
dw 0x000000
...

 

I have also added some *really* helpful info in the .zip file I attached to this post.  Some information on how code blocks are used in the DFB assebler and how to take advantage of the state optimizer, as well as some information on the instruction pielining and useful cheatsheets / code samples.

MrC
MrC's picture
User
13 posts

Thanks. This may be good.... Studying the material..... Standby Houston........

 

MrC

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