Datapath Super Primitives! | Cypress Semiconductor
Datapath Super Primitives!
Please welcome another four (four!) installments into the super primitive category, this time with the intent of getting you up and running with a datapath faster and easier than ever before. These four datapath super primitives eliminate 95% of the busywork associated with developing for a datapath and get you trying, testing and creating with PSoC’s powerful UDB datapaths in no time at all.
These datapath super primitives allow you to start designing with an 8, 16, 24 or 32 bit datapath, preconfigured and bristling with features to help you try out new ideas and debug when things go wrong. These super primitives provide you with a readymade component symbol, configurable component parameter (A0, A1, D0, D1 initializations right in the customizer, FIFO configuration of status reporting and easy access to the FIFO single buffer mode as well as optional debugging hardware signals and reset). Premade API files simplify component development with a header file containing all the necessary datpath registers, pointers, masks, modes and shifts already defined for you, as well as a C file that provides a Start() API ready to go with all the features you enable in the customizer.
Excited? I’m just getting started. These super primitives also include a skeleton verilog file, with all the necessary code to get started already included such as standard inputs and outputs, component parameters, a state machine and a preconfigured datapath of your choosing (8, 16, 24, or 32 bit). The preconfigured datapaths are already chained for you so they “just work” and include shifting setups for left shifts and arithmetic right shifts. The datapaths are also moved into the merge region of the verilog file, so when you add inputs and outputs to your symbol, simply re-generate your verilog file, and the new inputs and outputs are added for you automatically, with nothing lost!
I can tell you are ready to start using these super primitives, but I am not done packing the awesomeness into these components. These super primitives also come packaged with a component debug capability file, giving you incredibly easy access to the working registers of the datapath (A0, A1, D0, D1, even the FIFOs in single buffer mode), simplifying debug and reducing the headaches associated with learning the datapaths. And to top it all off, you also get a DMA capability file, giving the DMA wizard easy access to all your important registers, simplifying the setup of getting data into and out of your datapath component.
With these components, all you need to do to start using a datapath is import the desired super primitive, point the Datapath configuration tool at the premade verilog file, configure your datapath and write your verilog to control it and GO!
Please check out the included README PDF for detailed instructions on using the super primitives.