Custom component creation using verilog_Building Errors | Cypress Semiconductor
Custom component creation using verilog_Building Errors
I am trying to build a custom component using verilog on psoc creator 3.3 but after finishing my code writing and during building I am getting errors. Is there any difference in terms of syntax in psoc creator's verilog and general verilog?
I have attached my project along with pdf which I am using as a reference guide.