Status and controll registers usage | Cypress Semiconductor
Status and controll registers usage
Summary: 2 Replies, Latest post by Gautam Das on 16 Nov 2011 05:42 AM PST
Verified Answers: 0
14 Nov 2011 07:27 AM PST#1
I'm trying to implement a VME interface using a PSoC devices, but there are some things I would know.
- How a status and controll register are accessed from uC ?
- For example, If I use two 8bit status registers for reading a 16bit data bus, using the cortex-M3, the reading will be performed contemporarily or it needs two or more clock intervals?
- How they are mapped on PSoC?
- What type of internal bus they use?
- Could I associate the same variable at two or more status or controll registers?
- There is a way to choose to use the FIFO registers contained in the UDBs or it is the IDE that assign the internal resources?
Thanks in advance