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Status and controll registers usage | Cypress Semiconductor

Status and controll registers usage

Summary: 2 Replies, Latest post by Gautam Das on 16 Nov 2011 05:42 AM PST
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PDES's picture
10 posts


I'm trying to implement a VME interface using a PSoC devices, but there are some things I would know.

  • How a status and controll register are accessed from uC ?
  • For example, If I use two 8bit status registers for reading a 16bit data bus, using the cortex-M3, the reading will be performed contemporarily or it needs two or more clock intervals?
  • How they are mapped on PSoC?
  • What type of internal bus they use?
  • Could I associate the same variable at two or more status or controll registers?
  • There is a way to choose to use the FIFO registers contained in the UDBs or it is the IDE that assign the internal resources?


Thanks in advance

user_460349's picture
1362 posts

Your question involves understanding of how PSoC works. I suggest you go and download some simple projects to see how the internal stuffs works with PSoC, try a few examples should help you design what to do.

dasg's picture
Cypress Employee
730 posts



  • Control Register is used to control the digital system by the CPU. You can use the APIs _Write( ); a Status Register is used when the CPU needs to read the status of internal digital signals. The API used for this is _Read( )
  • There are Universal Digital Blocks (UDB) in PSoC3/5 which has a Status and a Control Register each. When a 16-bit parallel digital signal is to be read, then two Status Registers from two UDBs will be utilized. These has to be read as two 8-bit data by the CPU.
  • A PSoC3/5 can have a max of 24 UDBs. It depends on the part number used. Hence there are equal number of Status and Control registers as the number of UDBs present. For more details on the placement of these registers refer to the UDB section of the Technical Reference Manual (TRM) here
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