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Setup time violation | Cypress Semiconductor

Setup time violation

Summary: 1 Reply, Latest post by Bob Marlowe on 24 Jul 2016 11:09 PM PDT
Verified Answers: 0
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jasonkahana_1482786's picture
21 posts

I am getting the following warning when I compile a program for PSOC5LP


Warning-1366: Setup time violation found in a path from clock ( CyBUS_CLK ) to clock ( UART_IntClock ).


I am running a UART and a USBUART at the same time.  The UARTint clock is set at 460.8 kHZ (Desired) for a 57600 baud stream.  I have it set to use the internal clock.  

My USBUART is communicating with a computer (COM) and the UART is communicating with a PROC chip for Bluetooth.  I am also running an SPI line to a display.

I am running PLL_out at 48 MHz.  


Any reason why I'm getting this error?  The code seems to run fine, but I don't want any issues with long term stability.





user_1377889's picture
9300 posts

I am able to compile a similar project without warnings, can you please post your complete project, so that we all can have a look at all of your settings. To do so, use
Creator->File->Create Workspace Bundle (minimal)
and attach the resulting file.




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