Setup time violation | Cypress Semiconductor
Setup time violation
I am getting the following warning when I compile a program for PSOC5LP
Warning-1366: Setup time violation found in a path from clock ( CyBUS_CLK ) to clock ( UART_IntClock ).
I am running a UART and a USBUART at the same time. The UARTint clock is set at 460.8 kHZ (Desired) for a 57600 baud stream. I have it set to use the internal clock.
My USBUART is communicating with a computer (COM) and the UART is communicating with a PROC chip for Bluetooth. I am also running an SPI line to a display.
I am running PLL_out at 48 MHz.
Any reason why I'm getting this error? The code seems to run fine, but I don't want any issues with long term stability.