SAR ADC Clock Frequency issues | Cypress Semiconductor
SAR ADC Clock Frequency issues
Hi.. I'm facing a couple of funny problems...
I want to run my PSoC 5 as fast as possible, so I set the IMO to 48MHz and the PLL to 76MHz (the fastest it'll go with the error limits not exceeding 80MHz). The UART complains that the error in clock is too much. So I pulled down the IMO slower; the only possible setting is the slowest, i.e. 3MHz. so the first Q is
1. Is it ok to run the PLL this way? (3M input and 76M output?)
Then I added a pair of SAR ADCs, which now complain that the internal clock frequency is too high and can at most be 18MHz. I have selected external clocking and am providing 18M to it. (See attached). Now the only way to fix that is to slow my PLL down or use only IMO directly; thereby slowing the entire chip to a crawl.
2. What is the workaround?
Thanks in advance,