PSOC5LP Clock output creates power rail noise while "sweeping" through clock frequencies | Cypress Semiconductor
PSOC5LP Clock output creates power rail noise while "sweeping" through clock frequencies
I am working on a project that requires me to output a variable frequency squarewave as an excitation signal and sample a sensor's response with an ADC.
I am currently using a 16bit SAR ADC to sample my signal.
I have also connected a clock output to a GPIO pin for my excitation signal. To change the frequency, I send a command over UART which triggers the function:
Everything works as expected, however I see a bit of high frequency noise appear on my power rails, while "sweeping through frequencies" and this noise is carrying over into my analog circuitry.
Any ideas on how to fix this noise? Maybe it is a grounding issue, or an issue with the PSOC5LP dev kit? The noise level is much better when sampling only a single frequency.