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PSOC5 GPIO strange behavior | Cypress Semiconductor

PSOC5 GPIO strange behavior

Summary: 2 Replies, Latest post by Gautam Das on 21 Feb 2011 01:19 AM PST
Verified Answers: 0
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SeriouSerg's picture
4 posts

In my project I use PSOC5 FTK.

GPIO strange behavior has been detected. Two subsystems, two problems.
First - IR receiver, connected to P5[1]. In receive cycle (RC6 protocol) there are avalanche interrupt req., 1000 and more. GPIO settings ( CMOS, TTL, pull-up, pull-down and others ) have no effect. Pulses are clear, no noise, no jitter; fronts normal too.
Only with external shmitt trigger (74AHC14) RC receiver work normally. Pulses picture on oscilloscope (after shmitt and before) doesn't differ (omly one - after trigger fronts are little straight).

In second subsystem symptoms are similar. Quadrature encoder misses pulses. (1000 cpr encoder). On 100 full shaft evolutions there are 700 - 800 missed pulses. Oscilloscope picture is very good, no phase shift between channels, no jitter, no noise, fronts very clear. Good encoder. But it works only after 74AHC14 channels signal precondition.

I think, that PSOC5 is super sensitive to signal front duration.  Can anyone tell something about it?

user_44248544's picture
1 post

On the quadrature encoder issue, I can tell you that I also had similar problems in a prototype project with the StarterKit with this component working with a mechanical encoder (with RC filtered outputs). I got some improvement by adding two inverters into the TopDesign. I had also to play with some different clock frequencies to get the best results. Not perfect, but much better.

dasg's picture
Cypress Employee
730 posts



Can you let us know what is the Bus Clock frequency you are using?

In the latest version of PSoC Creator(PSoC Creator 1.0), there is a Sync Component. This can be used to synchronize the external signal with the system Clock. This will help eliminate the missing of counts.



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