You are here

PSoC 5LP SPI Master mode change | Cypress Semiconductor

PSoC 5LP SPI Master mode change

Summary: 5 Replies, Latest post by Asha Ganesan on 22 Oct 2013 01:11 AM PDT
Verified Answers: 0
Last post
Log in to post new comments.
squarez's picture
1 post

I have a design with 3 SPI devices on a common SPI bus. I used the information on the SPI _Master_v2_40 component data sheet to multiplex the Slave Select signals and this works fine. Now that I have a PCB in hand I am finding that 2 of the peripherals need different clock polarities. The F-RAM wants to sample the MOSI data on the rising edge of SCLK and the Multiplying DAC wants to sample the MOSI data on the falling edge.

I do not find any information on how to change this configuration other than in the .CYSCH page. The M-DAC does have a configuration bit that can be set so it will sample data on the rising edge but I need to initially talk to it using the falling edge to set this bit.

Is there a way to change the mode configuration from CPOL = 0 to CPOL =1 on the fly or is this only set when the application is generated?

user_119377051's picture
866 posts

Hi squarez
I couldn't find any API for change the clock phase,

And no control register for determine the clock phase.

And no clue from detail block diagram of SPI module.

Is it mean can't change the phase at the run time.

One idea comes up, that use Inverter logic at the MOSI line.

To use dedicated wiring to each device, FRAM and MDAC.

But, I couldn't know that the detail clock phase just meet with your devices.

user_119377051's picture
866 posts

Correct "MOSI line" to "SCLK line"

Didn't know why because clock phase has four different pattern.

user_1377889's picture
9256 posts

You could think of reverting the clock polarity together with the appropiate SS-signal and a bit of logic (XOR). I did not have a look into the sources yet, but parameters that cannot be changed by an API usually are hard-coded using #ifs.



user_460349's picture
1362 posts

 I think best is to rais a case to Cypress. 

Asha Ganesan's picture
Cypress Employee
33 posts

Hi squarez,

The SPIM component has been designed in such a way that it generates the corresponding verilog code depending on the mode you choose in the dialog box. Hence, the mode option is not run-time configurable. So, if you would want the component to work in 1 of 2 modes, whose selection you might change during run-time, it would be better if you use 2 separate SPIM modules: one configured to mode 0 and the other configured to mode 2. You can use a Digital Multiplexer to choose which set of SS, MOSI and MISO lines are to be connected to the IO pins.

The reason behind why I am recommending this option instead of modifying the SPIM block internally is because, in either case, the result would turn out to occupy same number of digital resources (datapaths and PLDs) and hence you will not find any significant difference between the two.

I hope this helps.

Thanks and Regards,

Log in to post new comments.