PSoC 5LP SPI Master mode change | Cypress Semiconductor
PSoC 5LP SPI Master mode change
I have a design with 3 SPI devices on a common SPI bus. I used the information on the SPI _Master_v2_40 component data sheet to multiplex the Slave Select signals and this works fine. Now that I have a PCB in hand I am finding that 2 of the peripherals need different clock polarities. The F-RAM wants to sample the MOSI data on the rising edge of SCLK and the Multiplying DAC wants to sample the MOSI data on the falling edge.
I do not find any information on how to change this configuration other than in the .CYSCH page. The M-DAC does have a configuration bit that can be set so it will sample data on the rising edge but I need to initially talk to it using the falling edge to set this bit.
Is there a way to change the mode configuration from CPOL = 0 to CPOL =1 on the fly or is this only set when the application is generated?