possible Verilog a1_init_a macro bug | Cypress Semiconductor
possible Verilog a1_init_a macro bug
at this time I wrote a DP verilog implementation and need to set A1 with a value != 0. If I check the Sim in Modelsim it is always 0. Can someone confirm this? My lines are shown here :
DP8 ( ...
If it realy a bug, how fast will it be fixed and distributed with the next update. Or even is there a work arround?