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Layout Guidelines for PSoC5 | Cypress Semiconductor

Layout Guidelines for PSoC5

Summary: 2 Replies, Latest post by Gautam Das on 19 Dec 2011 12:27 AM PST
Verified Answers: 0
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kabhijit's picture
32 posts

In the PSoC Family dasheet (Doc number 001-44094 Rev. *F), the layout guidelines are given on page 9.  In the accompanying figure (Fig. 2-5) it is not clear what is the electrical connection of C13 and C14. Moreover, pin 46 (which is a GPIO pin - P3[2]) seems to have a via on it which connects it to ground. Can someone please clarify what needs to be done?




user_66945721's picture
256 posts

 Yes,this puzzled me too initially,but if youre looking to build a PSoC based design,all you need is shown on the "Power System" diagram on Page 29.

Though do note,that its better to look at existing kit schematics,since this diagram isnt the whole picture.

dasg's picture
Cypress Employee
730 posts

Hi Abhijit,


Figure 2-4 shows the schematic for the PCB layout shown in figure 2-5.


According to the schematic, C13 and C14 are connected to P3[2] (pin 46) which is used as a bypass capacitor for the Delta Sigma ADC. There is an option in the ADC configuration Reference Section and "Internal Bypassed on P3.2".


The PCB layout snap is obscure in that portion. Thank you for bringing this to our notice.

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