Layout Guidelines for PSoC5 | Cypress Semiconductor
Layout Guidelines for PSoC5
In the PSoC Family dasheet (Doc number 001-44094 Rev. *F), the layout guidelines are given on page 9. In the accompanying figure (Fig. 2-5) it is not clear what is the electrical connection of C13 and C14. Moreover, pin 46 (which is a GPIO pin - P3) seems to have a via on it which connects it to ground. Can someone please clarify what needs to be done?