Detection capsense problem | Cypress Semiconductor
Detection capsense problem
I designed a board which contain 20 capsenses with a PSOC5LP CY8C5888LTI-LP097.
My problem is that when I touch one capsens like for example P0, several capsense P0,P0,P0,P0,P0 are activated also. It's like all the port 0[xx] is unsettle. I don't understand why, I tryed to respect design rules, I put capacitors on VDDIO as you can see in my schematic. I use 2 channels for capsense, so I put two CMOD 1u capacitor as in the datasheet.
The weird thing is that capsense's tracks are not close on the PCB but the capsense is activated (see my PCB image).
My track's width are 0.2mm with a cleareance of 0.19mm
So if you have any sugestions let me know