Changing LUT values exceeds design | Cypress Semiconductor
Changing LUT values exceeds design
I'm using the CY8CKIT-059 board for my evaluation.
Right now my design uses 79% of UDBs. It has many components in it, two of them are 5-in 6-out LUTs.
At some point I decided to change some values in them. After doing that I get the "E2071: Unable to pack the design into 24 UDBs. See the Digital Placement section of the report file for details. For additional assistance, see the Mapper, Placer, Router section in the PSoC Creator help".
I would like to stress that the only change between successful compilation and the above error is LUT values. All I have to do is clicking "Undo" once, and it compiles successfully again.
Why does this happen? How can I overcome this problem?