Hello, I could say that I'm doing wrong when I measure a sine signal using a filter and I get some voltage spikes are we of that wave
Can you please post your complete project, so that we all can have a look at all of your settings? To do so, use
Creator->File->Create Workspace Bundle (minimal)
and attach the resulting file.
here this file
I have no experiences with ADC configured as left align, Did you try using right align?
Looks like your signal us unsigned values and the filter is treating the values as signed.
That gives a spike at the signed rollover.
if you comment out the line 63 the voltage spikes disappear.
difficult to understand the work Filter_SetDalign () and Set Coherency ()
I did considering the filter Datasheet
solve the problem, change input range Vss to vdd
thank you for your help
No, this is not a solution.
The problem reappears at the increase of 32,768 over the input signal.
What happens if you increase the signal amplitude so that the mximum values goes above 33000?