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What's wrong with Sample And Hold in PSoC5LP | Cypress Semiconductor

What's wrong with Sample And Hold in PSoC5LP

Summary: 2 Replies, Latest post by danaaknight on 20 Oct 2013 06:52 AM PDT
Verified Answers: 0
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vlado14142's picture
1 post

 Hello, I have played with PSoC 5LP dev. kit and found very strange fenomenon with Sample and Hold component:

I'm using Sigma-Delta ADC 14bit mode, single mode, single sample to measure voltage on pot. R56 on the kit.

I use a timer to start S/H and the same timer to fire interrupt in which I mesure input signal (Just for checking - from potentiometer so it is constant). When I measure voltage before S/H it varies not more than 2 bits. If I measure it after S/H component then measured value varies to 5-6 bits.

Here is a part of code in interrupt:


CyDelayUs(1) ;// for testing
AMux_1_Select(0); // mux channel '0' is signal before S/H ; '1' - after

//  AMux_1_Select(1); // mux channel '1' - after S/H

 CyDelayUs(4) ;// for testing
ADC_IsEndConversion(ADC_WAIT_FOR_RESULT); // waiting for result from ADC - REF channel
temp_Value = ADC_GetResult32();

ADC_IsEndConversion(ADC_WAIT_FOR_RESULT); // waiting for result from ADC - REF channel
temp_Value = ( ADC_GetResult32() + temp_Value) / 2 ;

 ADC_StartConvert();// measure '0' channel 
REF_Voltage = ( ADC_GetResult32() + temp_Value)/2 ;



If I use AMux_1_Select(1) - the voltage is after S/H and the result is very strange - error is about 3-4 bits.

What can I do, so the S/H will be working normally?

 I need a simultaneous true measure of 3 different channels and14 bits is a must.

Thanks in advance.

user_1377889's picture
9301 posts

Usually it is advisable to upload a complete project so that we can check all the settings.

What I see at first sight are your delays in µs which can be a bit short for a MUX - S&H - ADC chain.



user_14586677's picture
7646 posts

The analog mux settling time shown in the datasheet is below, so first blush might

make you think you are allright. But it is not stipulated at what resolution, I will bet its

12 bit settling time. I will have that clarified. You could always run a quick test for your

actual layout, thats one of the beauties of PSOC, ability to self test.


Your A/D, set at 14 bits, if Vref was +/- 2.048, read range of 4.096, then 1 lsb = 250 uV.

So you would typically want settling to 1/2 or 1 lsb.


The S/H has an acquistition time of 1 uS, 1%, which is only ~ 7 bit performance.


In short Bob is spot on, delays look pretty small.


Regards, Dana.


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