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Warning 1361 | Cypress Semiconductor

Warning 1361

Summary: 1 Reply, Latest post by Bob Marlowe on 29 Oct 2014 08:15 AM PDT
Verified Answers: 0
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Manikkoth's picture
Cypress Employee
11 posts

I am getting a warning like this

" The design contains a combinational loop. Check the design for unintentional latches. Breaking the loop at "


can any one help me to understand this warning




user_1377889's picture
9307 posts

You have probably connected some gates (like forming an RS-FF) which may lead to warnings like that.

Easiest for us to help you is to post the complete project here.  To do so, use
Creator->File->Create Workspace Bundle (minimal)
and attach the resulting file.


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