Unable to maintain two timer's in Sync | Cypress Semiconductor
Unable to maintain two timer's in Sync
I am using two timers T1 and T2 with below configuration, I intend to configure them dynamically at different frequency, However to test i configured them both to generate an interrupt every 500usec.
T1 -> TC interrupt - Every 500 usec (Input clock - 10 MHz) UDB T2 -> TC interrupt - Every 500 usec (Input clock - 10 MHz) UDB
Timer's are enabled simultaneously(T1 followed by T2), and corresponding digital port's are toggled inside ISR's to measure the timing on scope. I made two observations here
1) Port 2(T2) is toggled with a delay of 7.8 usec w.r.t Port 1(T1)
2) Port 1/2 o/p repetition period - 500 ~2 ( plus minus 2 )
This timing is very crucial for my implementation. I am unable to achieve a consistent delay pattern. I have tried modifying timer 1 counter to compensate for initial delay as mentioned in point (1) above without any success.
Is there any other way to achieve it, I am struggling with multiple timer's. Can someone suggest an improvement or an alternative way to achieve it.
I am new new to PSoc and still learning ways to work with it. Any help is highly appreciated. Thanks