UDB Shift opertation fail | Cypress Semiconductor
UDB Shift opertation fail
I've been using the UDB editor with a 16-bit datapath to define a motor control block which takes speed and distance, and then sends the necessary pulses to a stepper motor driver. All was well until I wanted to add a "direction" bit.
In order to FIFO buffer the direction bit, it has to be appended to the MSB of my 'Distance' value. This value gets copied from FIFO to register D1 by my state machine followed by being copied to A1 prior to use. Here is where the problem arises:
To recover the MSB, I try to use instructions: ALUOut = A1 << 1 | 0, A1 = ALUOut followed by ALUOut = A1 >> 1 | 0, A1 = ALUOut. The bit that winds up in "Shift out (left)" does not match the value expected, and the value of the lower 15 bits seems to get corrupted.
Am I missing something with the >8 bit wide shift operations? I'm particularly confused because values less than 255 do NOT get corrupted, suggesting perhaps that something's going wrong with which bit is winding up in the shift output.. Unfortunately my understanding of the verilog code isn't great enough to see if there's a fault there.