UART TX and RX interrupts | Cypress Semiconductor
UART TX and RX interrupts
Hi, I'm new to PSOC and uC in general. I've used Atemga in the distant past but I pretty much forgot many concepts...
I just want to understand the theory here...
I'm implementing a UART in PSOC5 (CY8CKIT 001 dev kit).
I need to send 7-byte long messages to another circuit, which will, after about 100ns, return a 15-byte long answer.
I want to use an interrupt to indicate that a byte has been sent and another interrupt to receive the answer.
I configured the UART like so: buffers set to 16 bytes and 2 ISR components connected to the rx/tx_interrupt pins.
As far as I understand, when I have two interrupts with the same priority, in my case the TX interrupt will be generated at first, then after reading the status and clearing the interrupt, the program should jump to the second interrupt (RX received), read everything from the rx-fifo and return to main()... then if more bytes arrive, it will just jump tp the rx interrupt and repeat the reading process.... what do I need to do to accomplish this? Are there any example projects available with 2 interrupts acting like I described?
I hope my questions are clear, if not I'll be happy to explain myself :-)