Trying to drive SPI lines for STP1612PW05 chip | Cypress Semiconductor
Trying to drive SPI lines for STP1612PW05 chip
I'm trying to drive the SPI lines for a STP1612PW05 chip.
My new board has the STP1612PW05 pins SDI, SDO, CLK, and LE connected to the PSoC5 pins for SPI_Master_v2_20 pins mosi, miso, sclk, and ss, respectively.
The STP1612PW05 datasheet at
describes on pages 13-15 a method of using the duration of LE high to identify the [type of] command being set over the data line. I've never seen this done before and I'm not sure how to comply with this using the SPI_Master component.
Any and all help is greatly appreciated.
Here's how I perceive the situation, which could be right or wrong! STP1612PW05 datasheet page 15 figure 6 shows how LE is high for 0 to 1 rising clock edge when one wants to perform the "Data Latch" command, but is high for 2 to 3 rising clock edges when one wants to perform the "Global Latch" command.
I see no ability to do this in the SPI_Master. Rather than connecting STP1612PW05 LE pin from SPI_Master ss pin, I think I need to drive STP1612PW05 LE pin explicitly myself. Then, I'm wondering how do I then control both the width of the high LE pulse as well as the relative timing of it to the data coming out of the SPI_Master. I'm sure hoping I won't have to totally hand code all the SPI stuff! Furthermore, looking at the rest of figure 6, I'm not at all certain what the relative timing between LE and the data is supposed to be in general.