Strange problems when sampling GPIO ports | Cypress Semiconductor
Strange problems when sampling GPIO ports
For my PSoC challenge project, I need to sample a GPIO port (to have a logic analyzer). I encountered some strange behaviors when doing that. I'm using a combination of LUTs for the trigger logic, which are driven by 2 registers (one for the bit mask, one for the compare values). My test circuit is a 8-bit-counter, running with about 6 kHz. The port I'm trying to sample is P3 (since it is available on the prototyping area).
My first version was using DMA for the GPIO data to memory. When doing so, only the bits which are not selected for trigger comparision are transferred properly - all other bits are set to the trigger compare value. To make it even more strange - the counter output seems to be distributed to the non-masked bits (meaning the the first bit not selected for trigger gets counter Q0, the second non-selected gets Q1 and so on) - which clearly isn't how I have connected the wires.
When I replace all the DMA logic with just a simple PWM timer to generate interupts, and sample via a Port_Read() call, these problems go away, but all bits are inverted.
In both cases I have routed the internal signals back to another port, and connected another logic analyzer. These signals are always fine (not inverted, not mixed up).
Has someone an idea what might happen here?