SPI Problems | Cypress Semiconductor
Hey! I'm back again! Thanks for being some helpful in the past though!
I have been working recently on communicating with an off chip component over a SPI interface (mode 0,0). The problem that I am running into right now is the way that the SPI Master component regulates the Slave Clock and Slave Select. If I am doing one way communication with the device, everything is fine, the SPI Master drives Slave Select low and clocks the data out over the Master Out Slave In.
The problem that I am running into, is if I need to listen to a response directly after sending the data out. The problem is, Slave select gets driven high directly after I write the command to the slave and the slave clock is driven low. The device that I am talking to expects the slave clock to continue ticking as well as the slave select to stay low during the entire sequence.
Is there a way to tell the SPI Master to transmit an arbitrary number of bytes, and to keep the Slave Select driven low, and the clock operating normally over the entire transaction?