You are here

SPI: FIFO_FULL - Interrupt is not resetting after reading out FIFO by DMA | Cypress Semiconductor

SPI: FIFO_FULL - Interrupt is not resetting after reading out FIFO by DMA

Summary: 1 Reply, Latest post by Gautam Das on 05 Jul 2011 05:40 AM PDT
Verified Answers: 0
Last post
Log in to post new comments.
Reini's picture
1 post

Hello! I am new in PsoC and i have following problem:

A SPI - Slave receives 4 16-bit values and triggers an FIFO-Full interrupt. This interrupt triggers a DMA , which reads out the data out of the FIFO using following sourceadress: SPIS_RXDATA_PTR.

The DMA has 4 Bytes per Burst, length 2000 and request per burst = 1;

This works, the first 4 values gets saved correctly in a buffer-array, but the problem is, that the FIFO-Full interrupt stays high and doesn't return to zero! A new transmission is not possible anymore.

I have tried reading the data out of the SPI-Slave using SPIS_ReadRxData(). In this case the FIFO-Full interrupt returns to zero.

Do i miss anything? How is it possible to let the FIFO-Full interrupt return to zero after reading out 4 values by the dma?


Thanks a lot!

dasg's picture
Cypress Employee
730 posts

Hi Reini,


There is a code example on use of SPI with DMA which can be found at the following location:


Looking at your comment, I have some concerns:


1) Since 16 bit words (2-Bytes each) is being received, and 4 such words will cause an interrupt, shouldn't the DMA be configured for 8 Bytes per Burst?


2) The status register can be read using Interrupt (ISR) or one of TD of the DMA Channel. (I am not sure of this method).


3) Can you upload your project so that we can debug the issue?



Log in to post new comments.