SPI daisychaining | Cypress Semiconductor
Hello to everybody,
I have been foolish myself trying to put one Master SPI and two Slave SPI in daisychain. The idea was:
1. Both SPIS are loaded with some data,
2. Writing one dummy byte in the SPIM it would go out via MOSI to the first SPIS, while the bits are entering this component, the previously loaded data bits would be leaving the device via MISO which in turn might be feeeding the second SPIS, which would be doing the same. At the end of the Master writting cycle, inside the Master Rx might be the byte comming from the second SPIS and inside the second SPIS Rx would be the data loaded in the first SPIS. Writting another dummy byte in the MAster would make appear the second loaded byte in the Rx Master register. SS signal and MCLK being shared by both slave devices.
It seems that the Rx register is a different one that the Tx register and so the data entered is not reshifted to the output, making daisychaining impossible. Curiosly, if the slave components are not Started(), the thing semms to work OK.
Can somebody help me?