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(Solved) How to Generate 0Hz - 50Hz Squarewave from 0-5V ADC. Total 8 Channel | Cypress Semiconductor

(Solved) How to Generate 0Hz - 50Hz Squarewave from 0-5V ADC. Total 8 Channel

Summary: 19 Replies, Latest post by dukieames780829_2759421 on 08 Oct 2017 07:00 PM PDT
Verified Answers: 2
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user_202683688's picture
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42 posts

Please see the attached project. I am getting this error for the first time. In notice details it says:

The placer is not able to place all of the carry chains without backtracking. It fills one UDB bank to 15/16 and the other to 7/8 and cannot place the final 2-datapath chain. As a workaround, add a control file to the TopDesign component (in Workspace Explorer's Components tab) with the following lines: ATTRIBUTE placement_force OF \Timer_ADPActiveTime:TimerUDB:sT16:timerdp:u0\ : LABEL IS "U(2,0)"; ATTRIBUTE placement_force OF \Timer_OutputPeriod:TimerUDB:sT24:timerdp:u0\ : LABEL IS "U(3,1)"; ATTRIBUTE placement_force OF \Timer_OutputActiveTime:TimerUDB:sT24:timerdp:u0\ : LABEL IS "U(0,1)"; This will fill the datapaths in the second UDB bank and allow the placer to assign the remaining datapaths.

1. Is it a problem of UDB? How to solve it?

2. I have already reduced requirement from 8*32bit Counter to 8*24Bit Counter.

Project Details:

8 Channel Analog (0V-5V, 10bit ADC) into 8 Channel Square wave output (0Hz - 50Hz, 50% duty cycle , step of 0.05Hz, tolerance +-0.005Hz).

user_242978793's picture
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1485 posts

I set the first device Counter one to 16 bit instead of 24 bit and the program compiled.  It appears that you are exceeding the resources of the part.  Here is the Tech reference manual on the part.

user_342122993's picture
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804 posts

My guess your project does not fit 24 UDB. 8x 24-bit counters take 8x3=24 UDB, and nothing left for ADC & etc. Try to reduce (some) counters to 16-bit, which should be sufficient for 50+/-0.005 Hz tolerance.  

Ok. bobgoar has faster fingers. I will delete my post...

user_1377889's picture
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10803 posts

You are busted ;-)

You are using 8 counters each 3 UDBs which sums up to 24 UDBs, the maximum of a PSoC5. On page 1 you still are using some more components that require more resources.

 

Bob

user_342122993's picture
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804 posts

Welcome to the party!!!

user_1377889's picture
User
10803 posts

Yeah, let's play blackjack, I know who tends to get busted... ;-)

 

Bob

user_202683688's picture
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42 posts

Thank you everyone for your support

-----

My guess your project does not fit 24 UDB. 8x 24-bit counters take 8x3=24 UDB, and nothing left for ADC & etc. Try to reduce (some) counters to 16-bit, which should be sufficient for 50+/-0.005 Hz tolerance.  

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I have calculated for 24Bit and 16Bit Freq division, but the problem is +/- 0.005Hz is not achieved, As for 24bit, I can have 1MHz base clock freq, but for 16Bit I must go for 6KHz Clock freq. I have attached a excel sheet for the same. Please comment on that, if I can make some better change.

user_342122993's picture
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804 posts

I will research it on weekends. I am thinking of two approaches: (i) dithered PWM, (ii) 8x16-bit DDS.

user_202683688's picture
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42 posts

Thank you.

I have changed the topic, as there is different discussion needed. Please suggest if I need to terminate/solved this thread and start new thread instead.

---

8 Channel Analog (0V-5V, 10bit ADC) into 8 Channel Square wave output (0Hz - 50Hz, 50% duty cycle , step of 0.05Hz, tolerance +-0.005Hz).

---

Please comment about it, as I have already attached project and my Idea and calculation in excel sheet. I am also learning about dithered PWM and DDS. Meanwhile there is interesting post about 24bit DDS by odissey1 here:

http://www.cypress.com/forum/psoc-community-components/dds24-24-bit-dds-...

user_342122993's picture
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804 posts

DhruvAcharya,

I briefly looked into problem and managed to save half resources using 8 24-bit DDS modules (see picture below). There no escape - any 24-bit DDS will use 3 UDB. But there is a trick: out of 8 DDS modules 4 were were implemented exclusively in PLD (no datapath was used), and 4 were implemented using a datapath. In result, only 50% of PLD resources and 50% of datapath resources were used, and entire project consumes only 50% of UDB resources.

I am not posting project yet, as I have not tested it. You can find DDS component implemented in PLD here:

http://www.cypress.com/forum/psoc-community-components/dds24-24-bit-dds-...

 

and another DDS component implemented by <kabron> in Datapath here: (searching for link...) 

    

   

user_1377889's picture
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10803 posts

Well, the "tolerance" is based on your Frequency stability, so I would suggest you to use a crystal to generate a precise HFCLK.

Your "step" of 0.05Hz just shows that you need a clock of not less than 50kHz, that is a precision of 1 permil which shows that you will need 12 bit resolution of the ADC to be on the safe side.

The GPIO-pins and the ADC do not work very precise at the rail-to-rail ends. The (very precise internal reference (use bypassed) will not allow for precise measures up to 5V. So I would suggest you to reduce and level-shift your incoming signal using a resistor ladder to a reasonable value. A later calibration of your ADC will sharpen the result.

The frequency generators can be built using 16 bit timers / PWMs which then will fit into the 24 UDBs of your PSoC5.

 

Bob

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