Sigma Delta Converter On Top | Cypress Semiconductor
Sigma Delta Converter On Top
Through some option exploring, I attempted the use of both the PSOC's internal and TI serial based ADS7818 converters. I started messing with the Sigma Delta converter and concluded its noise immunity suits my application best.
Therfore, I can sample at a lower rate, average less, and use less memory when transmitting samples over UARTs.
The one drawback is the PSOC 5 only has 1 Sigma Delta converter, and I need to monitor two shunts. There is a sequencing SAR converter, but no sequencing Sigma Delta. An app note I found suggested using the analog mux.
The attached project shows how I implemented it. I am receiving an asynchronus path warning. I am thinking using a clock to control the select object is not the best idea? Prior to every edge of the ACLK, the mux alternates between channels 0 and 1. The DMA thus stores every other sample as one shunt's reading, and the other offset, the other shunt. Is there a better way of sequencing? Despite the warning, the system appears to be working, but I may be paying some kind of noise penalty.