Setup time violation emFile_1_Clock_1 | Cypress Semiconductor
Setup time violation emFile_1_Clock_1
As mentionned in a previous topic, I get a warning after building my project:
"Warning-1366: Setup time violation found in a path from clock ( emFile_1_Clock_1 ) to clock ( emFile_1_Clock_1 ).The static timing analyzer reported a warning. See the warning message for details. Additional information may be available in the timing report file." (see attached pdf)
Should I worry about it? If yes, how do I fix it?